Position: Silicon Design Package Engineer
Location - Santa Clara, CA
Contract
This role is highly specialized in semiconductor packaging design, requiring strong EDA tool proficiency and knowledge of advanced packaging technologies
Tools & Knowledge:
Mentor/Siemens and Cadence tools (especially for Package Layout Automation - PLA).
Technical Expertise:
Multi-layer package design experience.
Understanding of substrate manufacturing Design Rules and Assembly Rules.
Familiarity with SIPI (Signal Integrity & Power Integrity) Rules.
Flip-chip package design concepts
#SiliconDesign #PackageEngineer #SemiconductorJobs #SemiconductorPackaging #EDAEngineer #MentorGraphics #SiemensEDA #CadenceTools #PackageLayoutAutomation #PLAEngineer #FlipChipDesign #AdvancedPackaging #ICPackaging #ChipPackaging #SubstrateDesign #SubstrateEngineering #DesignRules #AssemblyRules #SIPIRules #SignalIntegrity #PowerIntegrity #SIPIEngineer #MultiLayerPackage #PackagingLayout #ChipDesignJobs #ElectronicDesignAutomation #TechJobsUSA #HardwareEngineer #ICSubstrate #SystemInPackage #SiPDesign #PackagingEngineer #SantaClaraJobs #SemiconductorEngineering